TOPOGRAPHIES OF SEMICONDUCTORS
1. PROTECTABLE SUBJECT MATTER
They protect the topography of a semiconductor product, that is to say, the layout of the different layers and elements that comprise an integrated circuit, its three-dimensional arrangement and its interconnections. Their protection is governed by Spanish Law 11/1988 of 3rd May for the legal protection of the topographies of semiconductor products.
2. TERM OF PROTECTION.
10 years from the end of the year during which the topography was registered or during which use of it was made in any country of the world.
3. PROSECUTION.
The application is examined by the SPTO in respect of formal requirements and thereafter, its grant is published in the Industrial Property Official Gazette.
